1. Field of the Invention
The present invention generally relates to RAMs (Random Access Memory), and particularly relates to a DRAM (Dynamic Random Access Memory) which can carry out a self-refresh operation.
2. Description of the Prior Art
A block diagram of a DRAM of the prior art is shown in FIG. 1. In FIG. 1, the DRAM comprises a memory cell array unit 1, which includes a memory cell 2, a capacitor 3 for electric charge, an n-channel MOS (Metal Oxide Semiconductor) transistor 4 functioning as a transfer gate, a word line WL, and a bit line BL.
The DRAM further comprises an address buffer/pre-decoder unit 5. The address buffer/pre-decoder unit 5 includes an address buffer for reading an address signal and a pre-decoder for pre-decoding a row address signal which is part of the address signal read by the address buffer.
The DRAM further comprises a row decoder 6, column decoder 7, a sense amplifier circuit 8, and an I/O gate 9. The row decoder decodes a pre-decode signal provided from the pre-decoder of the address buffer/pre-decoder unit 5 so as to select one among many word lines WL. The column decoder 7 decodes a column address signal provided from the address buffer of the address buffer/pre-decoder unit 5 so as to supply a column selection signal for selecting a column. The sense amplifier circuit 8 amplifies signals read from the memory cell array unit 1, and the I/O gate 9 selects a column on the basis of the column selection signal provided by the column decoder 7.
The DRAM further comprises a data output buffer 10, a data input buffer 11, and a write-clock generator 12. The data output buffer 10 latches data read from the memory cell array unit 1 so as to provide output data DO1-DO4, where /OE ("/" is used herein for indicating that the signal is that of a negative logic) is an output enable signal provided externally for controlling the data output buffer 10. The data input buffer 11 reads and stores data to be written which is provided externally. The write-clock generator 12 provides a write-clock signal for controlling the operation of the data input buffer 11, where /WE is a write enable signal provided externally for controlling a write operation.
The DRAM further comprises a substrate bias generator 13 for generating a substrate bias voltage, a refresh address counter 14 for providing an address signal used in a refresh operation, a self-refresh circuit 15 used for a self-refresh operation. The self-refresh circuit 15 includes an oscillator 16, a substrate bias generator 17, a timing circuit 18, a frequency divider 19, and an AND gate 20.
The DRAM further comprises a clock generator 21 for supplying a clock signal to the row decoder 6, the sense amplifier circuit 8, the substrate bias generator 13, etc. The DRAM further comprises a clock generator 22 for supplying a clock signal to the address buffer of the address buffer/pre-decoder unit 5, the column decoder 7, the write-clock generator 12, etc. Here, /RAS is a row address strobe signal, and /CAS is a column address strobe signal, both provided externally.
The DRAM further comprises a mode controller 23. When selecting a CBR (CAS Before RAS) refresh mode on the basis of a clock signal provided by the clock generator 21 and the column address strobe signal /CAS, the mode controller 23 sends the CBR refresh mode signal .O slashed..sub.CBR to the self-refresh circuit 15.
In FIG. 1, VCC is an external power voltage level such as for example 3.3 V, and VSS is a ground level of 0 V, both provided externally.
FIG. 2 shows signals when the DRAM is operating in a normal operation mode. As shown in FIG. 2, a normal operation mode is carried out when the column address strobe signal /CAS changes from a high level to a low level after the row address strobe signal /RAS changes from the high level to the low level.
FIG. 3 shows signals when the DRAM is operating in a refresh mode. As shown in FIG. 3, the CBR refresh mode is enacted when the column address strobe signal /CAS changes from the high level to the low level after the row address strobe signal /RAS changes from the high level to the low level.
Actually, the self-refresh mode is enacted when 100 .mu.sec passes after the above signal changes while both of the /CAS and /RAS signals stay at the low level. Each self-refresh operation is carried out at a predetermined interval such as for example 16 .mu.sec.
In FIG. 3, .O slashed..sub.OSC is a signal provided by the oscillator 16, and .O slashed..sub.SR is a signal provided by the AND gate 20 for controlling self-refresh cycles.
In the DRAM shown in FIG. 1, the external power voltage level VCC is provided for all the components mentioned above not only when the DRAM is operating in the normal operation mode but also when it is operating in the self-refresh mode. Thus, the electric power consumed by the DRAM tends to be large, which raises a problem of shortening the life of back-up battery when such DRAM is used for portable equipment such as personal computers of laptop types.
In order to obviate this problem, a voltage step-down circuit 25 is provided in a DRAM of the prior art, as shown in FIG. 4, for providing the self-refresh circuit 15 with a lowered voltage level VII which is made by lowering the voltage level of the power voltage level VCC. In this manner, an electric power consumption in the DRAM is reduced in the prior art. Here, a level conversion circuit 26 provided in the self-refresh circuit 15 converts the VII level of the self-refresh cycle signal .O slashed..sub.SR from the AND gate 20 into the VCC level (the external power voltage level).
In the DRAM shown in FIG. 4, the electric power consumption of the self-refresh circuit 15 can be reduced, and the overall electricity consumption can be lowered. Such amount of a reduction in electricity consumption as achieved by this method, however, is not sufficient for such DRAM to be able to be used in portable equipment like laptop personal computers. Thus, a further reduction in electricity consumption needs to be achieved.
While FIG. 3 is used for the description of the self-refresh mode of the DRAM of FIG. 1, a transition from the normal operation mode to the self-refresh mode is slightly different for another type of DRAMs. That is, FIG. 3 shows the activation of the self-refresh mode of an asynchronous DRAM, which is differs from that of a SDRAM (Synchronous DRAM). Unfortunately, using a SDRAM rises another problem as will be described below.
In DRAMs, a timer is necessary for controlling a refresh operation. In order for this timer to be accurate within a tolerance level, the oscillation frequency of the oscillator must be a right frequency. For assuring this, the oscillator is designed to allow a fine adjustment of a oscillation frequency by the cutting off of its fuses. As a step to be taken before this adjustment of the oscillation frequency, however, the cycle of the output signal of the counter should be measured.
When using an asynchronous DRAM, measuring the cycle of the counter output signal is carried out by utilizing a mode which is called a counter test cycle.
FIG. 5 shows signals for explaining the method of measuring the cycle of the counter output signal.
In order to measure the cycle of the counter output signal by using the counter test cycle, the column address strobe signal /CAS is changed from the high level to the low level, and, then, the row address strobe signal /RAS is changed from the high level to the low level.
As described before with reference to FIG. 3, the CBR cycle is set by the changes of the signal levels described above. When a predetermined length of time such as for example 100 .mu.sec passes without any changes in the signal levels, the self-refresh cycle is enacted, where the output of the data output buffer is made a high impedance state, thus prohibiting the output of any data. When the CBR cycle is set, the counter start keeping count of the oscillator output, and measures 100 .mu.sec from the moment when the row address strobe signal /RAS became the low level.
If the column address strobe signal /CAS is made the high level again after the setting of the CBR cycle, and if the column address strobe signal /CAS is changed to the low level again before the 100 .mu.sec passes, the output of the data output buffer becomes a data output state as shown in FIG. 5.
On the other hand, even if the column address strobe signal /CAS is changed to the low level again after the 100 .mu.sec passes, the output of the data output buffer is made a high impedance state. This is because the self-refresh cycle has been already enacted by this point of time.
Suppose measuring the output state of the data output buffer while gradually delaying the change of the column address strobe signal /CAS from the high level to the low level. At first, the output state should be the data output state. Then, the change of the column address strobe signal /CAS is delayed step by step until the output state becomes the high impedance state. With this condition, the time difference between the time of the row address strobe signal /RAS changing to the low level and the time of the column address strobe signal /CAS changing second time to the low level is the length of time which is recognized to be 100 .mu.sec by the counter.
In this manner, the 100 .mu.sec which the counter measures using its own clock signal can be measured, so that one cycle of the counter output signal can be known in the actual time scale. Since the counter is comprised of a frequency divider, the oscillating frequency of the oscillator can be calculated by taking into account the frequency dividing ratio of the frequency divider. Then, the oscillating frequency of the oscillator can be adjusted to obtain a proper cycle of the counter output signal.
However, differing from asynchronous DRAMs, SDRAMs start a self-refresh operation having a cycle such as for example 16 .mu.sec immediately upon receiving a self-refresh instruction as a mode selection instruction.
Accordingly, it is impossible for SDRAMs to set a counter test cycle as in asynchronous DRAMs, and the problem is that there is no easy method of measuring the cycle of the counter output signal for SDRAMs.
Accordingly, there is a need in the field of the DRAM for a DRAM in which the consumption of electric power can be further reduced so that a back-up battery can be used for a longer time when such DRAM is used for portable equipment such as laptop type personal computer, thus enhancing the usefulness of such equipment.
Also, there is a need in the field of the DRAM for a DRAM which provides a simple method of measuring a cycle of the counter output signal so that the oscillating frequency of an oscillator can be adjusted to obtain a proper cycle of the counter output signal.